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» An O(nlogn) time algorithm for optimal buffer insertion
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DAC
2006
ACM
14 years 8 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
NANONET
2009
Springer
200views Chemistry» more  NANONET 2009»
14 years 1 months ago
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approa...
Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli
GD
2006
Springer
13 years 11 months ago
Planarity Testing and Optimal Edge Insertion with Embedding Constraints
The planarization method has proven to be successful in graph drawing. The output, a combinatorial planar embedding of the so-called planarized graph, can be combined with state-o...
Carsten Gutwenger, Karsten Klein, Petra Mutzel
DAC
2011
ACM
12 years 7 months ago
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...
Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, ...
CONCUR
2010
Springer
13 years 8 months ago
Buffered Communication Analysis in Distributed Multiparty Sessions
Many communication-centred systems today rely on asynchronous messaging among distributed peers to make efficient use of parallel execution and resource access. With such asynchron...
Pierre-Malo Deniélou, Nobuko Yoshida