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» An O(nlogn) time algorithm for optimal buffer insertion
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ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
14 years 4 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
HIPEAC
2010
Springer
13 years 5 months ago
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors
Abstract. Stream programming is a promising way to expose concurrency to the compiler. A stream program is built from kernels that communicate only via point-to-point streams. The ...
Paul M. Carpenter, Alex Ramírez, Eduard Ayg...
ICDE
2007
IEEE
125views Database» more  ICDE 2007»
14 years 1 months ago
Improved Buffer Size Adaptation through Cache/Controller Coupling
Database workloads seldom remain static. A system tuned by an expert for the current environment, might not always remain optimal. To deal with this situation, database systems ha...
Christian A. Lang, Bishwaranjan Bhattacharjee, Tim...
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 4 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt
DAC
2004
ACM
14 years 8 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...