203 search results - page 6 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
ASPDAC
2004
ACM
14 years 25 days ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, t...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. Our algorithm minimizes area under required timing a...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...