2927 search results - page 579 / 586 » An OR Parallel Prolog Model for Distributed Memory Systems |
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
IEEEPACT
2003
IEEE
14 years 24 days ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
CLUSTER
2009
IEEE
14 years 2 months ago
2009
IEEE
—Server consolidation based on virtualization technology will simplify system administration, reduce the cost of power and physical infrastructure, and improve utilization in tod...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
ICPP
2002
IEEE
14 years 13 days ago
2002
IEEE
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...