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DAC
2002
ACM
14 years 8 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
14 years 8 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
ARC
2008
Springer
141views Hardware» more  ARC 2008»
13 years 9 months ago
A Parallel Hardware Architecture for Image Feature Detection
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architect...
Vanderlei Bonato, Eduardo Marques, George A. Const...
HICSS
2006
IEEE
121views Biometrics» more  HICSS 2006»
14 years 1 months ago
Enterprise Architecture: A Social Network Perspective
IS Architecture emerges as a result of a sequence of IS project implementations. The architecture that emerges can be viewed as a network of software components linked by their in...
David Dreyfus, Bala Iyer
ISLPED
2007
ACM
123views Hardware» more  ISLPED 2007»
13 years 9 months ago
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ ) f...
Sushu Zhang, Karam S. Chatha, Goran Konjevod