We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architect...
Vanderlei Bonato, Eduardo Marques, George A. Const...
IS Architecture emerges as a result of a sequence of IS project implementations. The architecture that emerges can be viewed as a network of software components linked by their in...
We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ ) f...