35 search results - page 7 / 7 » An analytical model for negative bias temperature instabilit... |
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...
INFOCOM
2000
IEEE
13 years 12 months ago
2000
IEEE
— End-to-end congestion control mechanisms such as those in TCP are not enough to prevent congestion collapse in the Internet (for starters, not all applications might be willing...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...