75 search results - page 3 / 15 » An efficient approach to simultaneous transistor and interco... |
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
— Circuit placement has a large impact on all aspects of performance; speed, power consumption, reliability, and cost are all affected by the physical locations of interconnected...
ISPD
2000
ACM
14 years 1 months ago
2000
ACM
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...
TCAD
2008
13 years 9 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
ICCD
2006
IEEE
14 years 6 months ago
2006
IEEE
— Continued scaling of CMOS has lead to a problem of scale as gates are faster than light travelling across a chip. Scalability used to be the hallmark of CMOS. Half the size, do...
JMLR
2010
13 years 3 months ago
2010
We propose a novel application of the Simultaneous Orthogonal Matching Pursuit (SOMP) procedure to perform variable selection in ultra-high dimensional multiple output regression ...