— Circuit placement has a large impact on all aspects of performance; speed, power consumption, reliability, and cost are all affected by the physical locations of interconnected...
Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi...
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
— Continued scaling of CMOS has lead to a problem of scale as gates are faster than light travelling across a chip. Scalability used to be the hallmark of CMOS. Half the size, do...
We propose a novel application of the Simultaneous Orthogonal Matching Pursuit (SOMP) procedure to perform variable selection in ultra-high dimensional multiple output regression ...