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VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 8 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
13 years 11 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
DATE
2010
IEEE
127views Hardware» more  DATE 2010»
14 years 14 days ago
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
— Pattern recognition has many applications in design automation. A generalized pattern recognition algorithm is presented in this paper which can efficiently extract similar pat...
Jason Cong, Hui Huang, Wei Jiang
DAC
2006
ACM
14 years 8 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang