257 search results - page 6 / 52 » An optimal algorithm for area minimization of slicing floorp... |
ICCAD
1990
IEEE
13 years 12 months ago
1990
IEEE
We present a hierarchicaltechniquefor floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative po...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...