192 search results - page 36 / 39 » Analysis and Prediction of Performance for Evolving Architec... |
BMCBI
2007
13 years 9 months ago
2007
Background: This work explores the quantitative characteristics of the local transcriptional regulatory network based on the availability of time dependent gene expression data se...
DSD
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
SIGCOMM
2004
ACM
14 years 2 months ago
2004
ACM
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
SIGCOMM
2005
ACM
14 years 2 months ago
2005
ACM
Hash table is used as one of the fundamental modules in several network processing algorithms and applications such as route lookup, packet classification, per-flow state manage...