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DAC
2004
ACM
14 years 8 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
ICCD
2006
IEEE
119views Hardware» more  ICCD 2006»
14 years 4 months ago
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling
— This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced...
Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. I...
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
14 years 1 months ago
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
DAC
2005
ACM
13 years 9 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 2 months ago
Use of statistical timing analysis on real designs
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
A. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gr...