115 search results - page 15 / 23 » Analysis and optimization of gate leakage current of power g... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
— For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit char...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
MJ
2007
13 years 7 months ago
2007
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wi...