115 search results - page 18 / 23 » Analysis and optimization of gate leakage current of power g... |
CARDIS
2004
Springer
14 years 1 months ago
2004
Springer
CMOS gates consume different amounts of power whether their output has a falling or a rising edge. Therefore the overall power consumption of a CMOS circuit leaks information about...
TVLSI
2008
13 years 7 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
ISLPED
2010
ACM
13 years 8 months ago
2010
ACM
We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...