Sciweavers

562 search results - page 13 / 113
» Analysis of Hardware Acceleration in Reconfigurable Embedded...
Sort
View
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 11 months ago
GRAAL - A Development Framework for Embedded Graphics Accelerators
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framewo...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
14 years 8 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
ICCAD
2002
IEEE
124views Hardware» more  ICCAD 2002»
14 years 4 months ago
Interface specification for reconfigurable components
This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a rec...
Satnam Singh
FPL
2010
Springer
174views Hardware» more  FPL 2010»
13 years 5 months ago
ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing
Researchers in embedded and reconfigurable computing are often hindered by a lack of suitable benchmarks with which to accurately evaluate their work. Without a suitable benchmark ...
Daniel W. Chang, Christipher D. Jenkins, Philip C....
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 1 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...