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DAC
2004
ACM
14 years 10 months ago
A frequency relaxation approach for analog/RF system-level simulation
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and...
Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, ...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 3 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 3 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
PADS
2003
ACM
14 years 3 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 4 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...