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FPGA
2011
ACM
321views FPGA» more  FPGA 2011»
14 years 7 months ago
An analytical model relating FPGA architecture parameters to routability
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
Joydip Das, Steven J. E. Wilton
ARVLSI
1995
IEEE
146views VLSI» more  ARVLSI 1995»
15 years 7 months ago
Array-of-arrays architecture for parallel floating point multiplication
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
H. Dhanesha, K. Falakshahi, Mark Horowitz
VLSID
2006
IEEE
153views VLSI» more  VLSID 2006»
16 years 4 months ago
An Asynchronous Interconnect Architecture for Device Security Enhancement
We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the mo...
Simon Hollis, Simon W. Moore
RULEML
2005
Springer
15 years 9 months ago
A Realistic Architecture for the Semantic Web
In this paper we argue that a realistic architecture for the Semantic Web must be based on multiple independent, but interoperable, stacks of languages. In particular, we argue tha...
Michael Kifer, Jos de Bruijn, Harold Boley, Dieter...
137
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FPGA
2009
ACM
151views FPGA» more  FPGA 2009»
15 years 10 months ago
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and ...
Alastair M. Smith, Steven J. E. Wilton, Joydip Das