4330 search results - page 735 / 866 » Analyzing security architectures |
138
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VLSID
2005
IEEE
16 years 4 months ago
2005
IEEE
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
135
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VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
185
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HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
127
Voted
HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
108
Voted
HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...