Sciweavers

50 search results - page 6 / 10
» Annealed MAP
Sort
View
PDP
2011
IEEE
12 years 11 months ago
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
Jia Huang, Christian Buckl, Andreas Raabe, Alois K...
ASPLOS
2006
ACM
14 years 1 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
DFMA
2005
IEEE
150views Multimedia» more  DFMA 2005»
14 years 29 days ago
Real-Time Treatment Planning Optimisation for Brachytherapy
In this paper, we present an integrated system for real-time dose distribution calculation and treatment planning optimisation for brachytherapy of prostate cancer, with a special...
Simon Chatelain, Jean-Philippe Thiran, Valery-Oliv...
SIBGRAPI
1999
IEEE
13 years 11 months ago
Piecewise Trilinear Deformation of Tomographic Models
: In this work we introduce an iterative method that deforms brain models built from tomographic images. The deformation is used for normalization purposes: individual models are d...
Sílvio de Barros Melo
DAC
1994
ACM
13 years 11 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain