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IPPS
1996
IEEE
13 years 11 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
HPCA
2005
IEEE
14 years 7 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
EUROPAR
2009
Springer
13 years 11 months ago
Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations
Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and redu...
Sylvain Collange, David Defour, Yao Zhang
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
14 years 7 months ago
Application Specific Datapath Extension with Distributed I/O Functional Units
Performance of an application can be improved through augmenting the processor with Application specific Functional Units (AFUs). Usually a cluster of operations identified from th...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
DAC
2001
ACM
14 years 8 months ago
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level syste...
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed...