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VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
CASES
2006
ACM
14 years 1 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
DAC
2008
ACM
14 years 8 months ago
Compiler-driven register re-assignment for register file power-density and temperature reduction
Temperature hot-spots have been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the ...
Xiangrong Zhou, Chenjie Yu, Peter Petrov
DSN
2007
IEEE
14 years 1 months ago
Using Register Lifetime Predictions to Protect Register Files against Soft Errors
— Device scaling and large integration increase the vulnerability of microprocessors to transient errors. One of the structures where errors can be most harmful is the register ...
Pablo Montesinos, Wei Liu, Josep Torrellas
ISLPED
1998
ACM
86views Hardware» more  ISLPED 1998»
13 years 11 months ago
The energy complexity of register files
Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue. The actual ...
Victor V. Zyuban, Peter M. Kogge