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GLVLSI
2010
IEEE
234views VLSI» more  GLVLSI 2010»
14 years 1 months ago
On-chip point-of-load voltage regulator for distributed power supplies
An ultra-low area, current efficient voltage regulator appropriate for distributed point-of-load voltage regulation in high performance integrated circuits (ICs) is described in t...
Selcuk Kose, Eby G. Friedman
DAC
1998
ACM
14 years 11 days ago
M32: A Constructive multilevel Logic Synthesis System
We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthe...
Victor N. Kravets, Karem A. Sakallah
DAC
2004
ACM
14 years 9 months ago
A frequency relaxation approach for analog/RF system-level simulation
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and...
Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, ...
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
14 years 5 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 5 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson