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DAC
2005
ACM
13 years 10 months ago
TCAM enabled on-chip logic minimization
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eï¬...
Seraj Ahmad, Rabi N. Mahapatra
DAC
2005
ACM
13 years 10 months ago
Response compaction with any number of unknowns using a new LFSR architecture
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
Erik H. Volkerink, Subhasish Mitra
DAC
2005
ACM
13 years 10 months ago
A green function-based parasitic extraction method for inhomogeneous substrate layers
This paper presents a new Green function-based approach for substrate parasitic extraction in substrates with inhomogeneous layers. This new formulation allows analysis of noise c...
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kar...
GLVLSI
2007
IEEE
153views VLSI» more  GLVLSI 2007»
13 years 9 months ago
Address generation for nanowire decoders
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
Jia Wang, Ming-Yang Kao, Hai Zhou
DAC
2010
ACM
13 years 9 months ago
Network on chip design and optimization using specialized influence models
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
Cristinel Ababei