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ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
14 years 2 months ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
14 years 2 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 2 months ago
Engineering trust with semantic guardians
The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trust...
Ilya Wagner, Valeria Bertacco
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
14 years 2 months ago
Estimating functional coverage in bounded model checking
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
Daniel Große, Ulrich Kühne, Rolf Drechs...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 2 months ago
A multi-core debug platform for NoC-based systems
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
Shan Tang, Qiang Xu