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DAC
1996
ACM
14 years 13 days ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
ISCAS
2002
IEEE
91views Hardware» more  ISCAS 2002»
14 years 1 months ago
Charge-based MOS correlated double sampling comparator and folding circuit
A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold ...
Roman Genov, Gert Cauwenberghs
GLVLSI
2006
IEEE
105views VLSI» more  GLVLSI 2006»
14 years 2 months ago
A practical approach for monitoring analog circuits
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
Mohamed H. Zaki, Sofiène Tahar, Guy Bois
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
14 years 21 days ago
DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits
In this paper, we develop a new standard cell placement tool, Dragon2000, to solve large scale placement problem effectively. A top-down hierarchical approach is used in Dragon200...
Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh
ICONIP
2007
13 years 9 months ago
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning
We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually co...
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asa...