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ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
14 years 20 days ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
DAC
2005
ACM
14 years 9 months ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu
ICCD
2005
IEEE
169views Hardware» more  ICCD 2005»
14 years 5 months ago
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
— Since rapid progress has been made in device improvement and integration of small carbon nanotube fieldeffect transistors (CNFETs) circuits, the time has come for developing c...
Wei Zhang, Niraj K. Jha
ISPD
2009
ACM
127views Hardware» more  ISPD 2009»
14 years 3 months ago
Synthesizing a representative critical path for post-silicon delay prediction
Several approaches to post-silicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit a...
Qunzeng Liu, Sachin S. Sapatnekar
IWANN
2005
Springer
14 years 1 months ago
CMOL CrossNets as Pattern Classifiers
This presentation has two goals: (i) to review the recently suggested concept of bio-inspired CrossNet architectures for future hybrid CMOL VLSI circuits and (ii) to present new re...
Jung Hoon Lee, Konstantin Likharev