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ISQED
2006
IEEE
85views Hardware» more  ISQED 2006»
14 years 2 months ago
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze T...
ISPD
2005
ACM
135views Hardware» more  ISPD 2005»
14 years 1 months ago
Recursive bisection placement: feng shui 5.0 implementation details
In this paper, we summarize circuit placement techniques and algorithms developed by the BLAC CAD research group; these have been integrated into our recursive bisection based pla...
Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden
DATE
2010
IEEE
104views Hardware» more  DATE 2010»
14 years 1 months ago
Large-scale Boolean matching
— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identif...
Hadi Katebi, Igor L. Markov
APCCAS
2002
IEEE
111views Hardware» more  APCCAS 2002»
14 years 1 months ago
Low-voltage high-speed PWM signal generations based on relaxation oscillator
This paper new two simple PWM (Pulse Width Modulation) signal generations based on modified relaxation oscillator are introduced. Their advantages of the proposed principle are th...
Montree Siripruchyanun, Paramote Wardkein
DATE
1999
IEEE
91views Hardware» more  DATE 1999»
14 years 16 days ago
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the Integrate...
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniota...