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ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
16 years 29 days ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
16 years 29 days ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
15 years 9 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
APCSAC
2006
IEEE
15 years 10 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
LCTRTS
2010
Springer
15 years 11 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...