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ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
13 years 11 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
FSE
2005
Springer
112views Cryptology» more  FSE 2005»
14 years 27 days ago
How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4 Processors
Abstract. This paper discusses the state-of-the-art software optimization methodology for symmetric cryptographic primitives on Pentium III and 4 processors. We aim at maximizing s...
Mitsuru Matsui, Sayaka Fukuda
FSE
2009
Springer
159views Cryptology» more  FSE 2009»
14 years 2 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
14 years 19 days ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos
RTCSA
2006
IEEE
14 years 1 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...