62 search results - page 10 / 13 » Applying Logic Synthesis for Speeding Up SAT |
PDP
2003
IEEE
14 years 1 months ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
ASPDAC
2007
ACM
13 years 12 months ago
2007
ACM
While the covering algorithm has been perfected recently by the iterative approaches, such as DAOmap and IMap, its application has been limited to technology mapping. The main fact...
ARITH
2009
IEEE
14 years 2 months ago
2009
IEEE
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...