62 search results - page 2 / 13 » Applying Logic Synthesis for Speeding Up SAT |
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Satisfiability (SAT) solvers often benefit from a preprocessing of the formula to be decided. For formulae in conjunctive normal form (CNF), subsumed clauses may be removed or par...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Functional decomposition is a fundamental operation in logic synthesis. Prior BDD-based approaches to functional decomposition suffer from the memory explosion problem and do not...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...