62 search results - page 7 / 13 » Applying Logic Synthesis for Speeding Up SAT |
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
ASPDAC
2007
ACM
13 years 12 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
CAV
2004
Springer
14 years 1 months ago
2004
Springer
The logic of equality with uninterpreted functions (EUF) and its extensions have been widely applied to processor verification, by means of a large variety of progressively more s...
ICCS
2005
Springer
14 years 1 months ago
2005
Springer
This paper proposes an innovative algorithm to find the two’s complement of a binary number. The proposed method works in logarithmic time (O(logN)) instead of the worst case li...