62 search results - page 8 / 13 » Applying Logic Synthesis for Speeding Up SAT |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
FROCOS
2005
Springer
14 years 1 months ago
2005
Springer
We describe results and status of a sub project of the Verisoft [1] project. While the Verisoft project aims at verification of a complete computer system starting with hardware a...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
EUROGP
2009
Springer
14 years 17 days ago
2009
Springer
The contribution presented herein proposes an adaptive genetic algorithm applied to quantum logic circuit synthesis that, dynamically adjusts its control parameters. The adaptation...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...