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FPL
2007
Springer
146views Hardware» more  FPL 2007»
14 years 2 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
IPPS
1998
IEEE
14 years 3 days ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
14 years 2 months ago
Application-aware prioritization mechanisms for on-chip networks
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chi...
IPPS
1999
IEEE
14 years 4 days ago
Mechanisms for Just-in-Time Allocation of Resources to Adaptive Parallel Programs
Adaptive parallel computations--computations that can adapt to changes in resource availability and requirement--can effectively use networked machines because they dynamically ex...
Arash Baratloo, Ayal Itzkovitz, Zvi M. Kedem, Yuan...
COGCOM
2010
112views more  COGCOM 2010»
13 years 5 months ago
Flexible Latching: A Biologically-Inspired Mechanism for Improving the Management of Homeostatic Goals
Controlling cognitive systems like domestic robots or intelligent assistive environments requires striking an appropriate balance between responsiveness and persistence. Basic goal...
Philipp Rohlfshagen, Joanna Bryson