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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 25 days ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee
MOBIWAC
2009
ACM
14 years 2 months ago
Protocol design and analysis of a HIP-based per-application mobility management platform
Rapid evolution of wireless networking has provided wide-scale of different wireless access technologies like Bluetooth, ZigBee, 802.11a/b/g, DSRC, 3G UMTS, LTE, WiMAX, etc. The c...
László Bokor, László T...
DSD
2006
IEEE
109views Hardware» more  DSD 2006»
14 years 1 months ago
ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems
Traditionally, an embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems difficult for many companies, a...
Tero Vallius, Juha Röning
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 1 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
FPL
2009
Springer
179views Hardware» more  FPL 2009»
13 years 11 months ago
Building heterogeneous reconfigurable systems using threads
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
Jason Agron, David L. Andrews