39 search results - page 5 / 8 » Architectural Modifications to Enhance the Floating-Point Pe... |
ERSA
2010
13 years 8 months ago
2010
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
DAC
2008
ACM
14 years 11 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
FPL
1995
Springer
14 years 1 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
ISCC
2009
IEEE
14 years 5 months ago
2009
IEEE
—This paper presents a reconfigurable architecture for the session initiation protocol (SIP). SIP is a protocol used primarily to establish point-to-point sessions between users...
FPL
2007
Springer
14 years 4 months ago
2007
Springer
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...