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» Architectural Specifications in CASL
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HPCA
2005
IEEE
14 years 11 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
HPCA
2003
IEEE
14 years 11 months ago
Reconsidering Complex Branch Predictors
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
Daniel A. Jiménez
HPCA
2003
IEEE
14 years 11 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
HPCA
2001
IEEE
14 years 11 months ago
Dynamic Thermal Management for High-Performance Microprocessors
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...
David Brooks, Margaret Martonosi
OSDI
2008
ACM
14 years 11 months ago
Taming Heterogeneous NIC Capabilities for I/O Virtualization
The recent emergence of network interface cards (NICs) with diverse hardware features for I/O virtualization poses an important challenge for virtual machine environments, particu...
Jose Renato Santos, Yoshio Turner, Jayaram Mudigon...