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» Architectural Support for Dynamic Memory Management
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CF
2009
ACM
14 years 3 months ago
Quantitative analysis of sequence alignment applications on multiprocessor architectures
The exponential growth of databases that contains biological information (such as protein and DNA data) demands great efforts to improve the performance of computational platforms...
Friman Sánchez, Alex Ramírez, Mateo ...
DAC
1997
ACM
14 years 26 days ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
ICASSP
2010
IEEE
13 years 6 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Althou...
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija...
HPCA
2006
IEEE
14 years 9 months ago
LogTM: log-based transactional memory
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan...
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
14 years 1 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...