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» Architectural Support for Synchronous Task Communication
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DAC
2008
ACM
14 years 8 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
INFOCOM
1995
IEEE
13 years 11 months ago
Measuring the Performance of Parallel Message-Based Process Architectures
Message-based process architectures are widely regarded as an effective method for structuring parallel protocol processing on shared memory multi-processor platforms. A message-b...
Douglas C. Schmidt, Tatsuya Suda
GLVLSI
2000
IEEE
69views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Supporting system-level power exploration for DSP applications
System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional b...
Luca Benini, Marco Ferrero, Alberto Macii, Enrico ...
TVLSI
2010
13 years 2 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
IADT
1998
100views more  IADT 1998»
13 years 8 months ago
Task Handling in Workflow Management Systems
Work ow management systems aim to automate the execution of business processes. One of the objectives of the work ow systems is to include the already existing applications such a...
Pinar Karagoz, Sena Nural Arpinar, Pinar Koksal, N...