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ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
13 years 11 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ICDE
2005
IEEE
154views Database» more  ICDE 2005»
14 years 8 months ago
Deep Store: an Archival Storage System Architecture
We present the Deep Store archival storage architecture, a large-scale storage system that stores immutable data efficiently and reliably for long periods of time. Archived data i...
Lawrence You, Kristal T. Pollack, Darrell D. E. Lo...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 2 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
DATE
2004
IEEE
105views Hardware» more  DATE 2004»
13 years 11 months ago
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
EVOW
2008
Springer
13 years 9 months ago
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...
Pedro A. Castillo, Antonio Miguel Mora, Juan Juli&...