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» Architectural descriptions for FPGA circuits
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DATE
2006
IEEE
94views Hardware» more  DATE 2006»
14 years 2 months ago
An analytical state dependent leakage power model for FPGAs
In this paper we present a state dependent analytical leakage power model for FPGAs. The model accounts for subthreshold leakage and gate leakage in FPGAs, since these are the two...
Akhilesh Kumar, Mohab Anis
ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
14 years 2 months ago
A low-complexity scanned-array 3D IIR frequency-planar filter
— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
Arjuna Madanayake, Leonard T. Bruton
FPGA
2004
ACM
145views FPGA» more  FPGA 2004»
14 years 2 months ago
Exploration of pipelined FPGA interconnect structures
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
CF
2004
ACM
14 years 2 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
14 years 2 months ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...