268 search results - page 6 / 54 » Architectural descriptions for FPGA circuits |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
DATE
2010
IEEE
14 years 18 days ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
JUCS
2007
13 years 7 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...