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MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
14 years 1 months ago
Compiling for instruction cache performance on a multithreaded architecture
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
Rakesh Kumar, Dean M. Tullsen
RAS
2010
137views more  RAS 2010»
13 years 7 months ago
Development of complex robotic systems using the behavior-based control architecture iB2C
This paper presents a development methodology for complex robotic systems using the behavior-based control architecture iB2C (integrated Behavior-Based Control). It is shown how a...
Martin Proetzsch, Tobias Luksch, Karsten Berns
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
14 years 2 months ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
TVLSI
2010
13 years 3 months ago
Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis
K-Means is a clustering algorithm that is widely applied in many fields, including pattern classification and multimedia analysis. Due to real-time requirements and computational-c...
Tse-Wei Chen, Shao-Yi Chien
COREGRID
2007
Springer
14 years 3 months ago
An Open Architecture for QoS Information in Business Grids
Abstract Grid Computing is now in the state of development that can offer dynamic management of various parameters that affect the applications’ properties such as performance an...
Konstantinos Tserpes, Dimosthenis Kyriazis, Andrea...