Compiling for instruction cache performance on a multithreaded architecture

Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven knowledge of procedure invocation patterns. On a multithreaded architecture, however, more conflicts may arise between threads than between procedures on the same thread. This research examines opportunities for the compiler to optimize instruction cache layout on a multithreaded architecture. We examine scenarios where (1) the compiler has knowledge about multiple programs that will be or are likely to be co-scheduled, and where (2) the compiler has no knowledge at compile time of which applications will be co-scheduled. We present solutions for both environments.

• Type: Conference
• Year: 2002
• Where: MICRO
• Authors: Rakesh Kumar, Dean M. Tullsen
• Keywords: Cache Aware Compilation, Hardware, Instruction Cache, MICRO 2002, Multithreaded Architecture