110 search results - page 12 / 22 » Architectural simulation for a programmable DSP chip set |
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
HIPC
2009
Springer
13 years 5 months ago
2009
Springer
Abstract--With General Purpose programmable GPUs becoming more and more popular, automated tools are needed to bridge the gap between achievable performance from highly parallel ar...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
TCAD
2002
13 years 7 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...