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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 4 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
PRIMA
2007
Springer
15 years 10 months ago
A Need for Biologically Inspired Architectural Description: The Agent Ontogenesis Case
Biologically inspired complex adaptive systems (BICAS) have and will continue to move from research laboratories into industry. As the ions presented by biologically inspired syste...
Terence L. van Zyl, Elizabeth Marie Ehlers
ICSE
2004
IEEE-ACM
16 years 3 months ago
A Hybrid Architectural Style for Distributed Parallel Processing of Generic Data Streams
Immersive, interactive applications grouped under the concept of Immersipresence require on-line processing and mixing of multimedia data streams and structures. One critical issu...
Alexandre R. J. François
MEMOCODE
2007
IEEE
15 years 10 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...
DAC
2007
ACM
16 years 4 months ago
Layered Switching for Networks on Chip
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
Zhonghai Lu, Ming Liu, Axel Jantsch