218 search results - page 11 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
FPL
1995
Springer
14 years 18 days ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
SBCCI
2006
ACM
14 years 3 months ago
2006
ACM
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
ISCAS
1999
IEEE
14 years 1 months ago
1999
IEEE
A new low-power design technique, multirate, has been used along with other methods such as look-ahead, pipelining in designing the cost-effective low-power architectures of video...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...