218 search results - page 23 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
HPCA
2000
IEEE
14 years 1 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
INFOCOM
2002
IEEE
14 years 1 months ago
2002
IEEE
A multigigabit IP router may receive several millions packets per second from each input link. For each packet, the router needs to find the longest matching prefix in the forw...
CORR
2002
Springer
13 years 8 months ago
2002
Springer
Despite recent excitement generated by the peer-to-peer (P2P) paradigm and the surprisingly rapid deployment of some P2P applications, there are few quantitative evaluations of P2...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...