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HPCA
2006
IEEE
14 years 9 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
14 years 27 days ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
CASES
2004
ACM
14 years 2 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
FASE
2007
Springer
14 years 3 months ago
Scenario-Driven Dynamic Analysis of Distributed Architectures
Abstract. Software architecture constitutes a promising approach to the development of large-scale distributed systems, but architecture description languages (ADLs) and their asso...
George Edwards, Sam Malek, Nenad Medvidovic
ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 5 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini