218 search results - page 36 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
DAC
2006
ACM
14 years 10 months ago
2006
ACM
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
ISCA
2011
IEEE
13 years 20 days ago
2011
IEEE
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
DBTEL
2001
Springer
14 years 1 months ago
2001
Springer
The DMTF’s recent work on management information modeling in the IP world has highlighted that a number of problems are still unsolved in this important area of enterprise manage...
DAC
2004
ACM
14 years 10 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...