1381 search results - page 85 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ICIP
1994
IEEE
14 years 9 months ago
1994
IEEE
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
EUROPAR
2009
Springer
14 years 25 days ago
2009
Springer
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
DAC
2003
ACM
14 years 1 months ago
2003
ACM
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...